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STK14C88-3
32Kx8 AutoStore nvSRAM FEATURES
* 35, 45 ns Read Access & R/W Cycle Time * Unlimited Read/Write Endurance * Automatic Non-volatile STORE on Power Loss * Non-Volatile STORE Under Hardware or Software Control * Automatic RECALL to SRAM on Power Up * Unlimited RECALL Cycles * 1 Million STORE Cycles * 100-Year Non-volatile Data Retention * Single 3.3V +0.3V Power Supply * Commercial and Industrial Temperatures * 32-Pin 300 mil SOIC and 600 mil PDIP Packages (RoHS-Compliant)
DESCRIPTION
The Simtek STK14C88-3 is a 256Kb fast static RAM with a non-volatile Quantum Trap storage element included with each memory cell. The SRAM provides the fast access & cycle times, ease of use and unlimited read & write endurance of a normal SRAM. Data transfers automatically to the non-volatile storage cells when power loss is detected (the STORE operation). On power up, data is automatically restored to the SRAM (the RECALL operation). Both STORE and RECALL operations are also available under software control. The Simtek nvSRAM is the first monolithic non-volatile memory to offer unlimited writes and reads. It is the highest performance, most reliable non-volatile memory available.
BLOCK DIAGRAM
Vcc A5 A6 A7 A8 A9 A11 A12 A13 A14 Quatum Trap 512 X 512 ROW DECODER STORE STATIC RAM ARRAY 512 X 512 RECALL STORE/ RECALL CONTROL V CAP
POWER CONTROL
HSB
SOFTWARE DETECT DQ 0 DQ 1 DQ 2 DQ 3 DQ 4 DQ 5 DQ 6 DQ 7 INPUT BUFFERS COLUMN I/O COLUMN DEC
A 13 - A 0
A 0 A 1 A 2 A 3 A 4 A 10
G E W
This product conforms to specifications per the terms of Simtek standard warranty. The product has completed Simtek internal qualification testing and has reached production status.
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STK14C88-3
VCAP A14 A12 A7 A6 A5 A4 A3 NC A2 A1 A0 DQ0 DQ1 DQ2 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Portagee Joe
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
VCC HSB W A13 A8 A9 A11 G NC A10 E DQ7 DQ6 DQ5 DQ4 DQ3
(TOP)
32-Pin SOIC 32-Pin PDIP
PIN DESCRIPTIONS
Pin Name A14-A0 DQ7-DQ0 E W G VCC HSB Input I/O Input Input Input Power Supply I/O I/O Description Address: The 15 address inputs select one of 32,768 bytes in the nvSRAM array Data: Bi-directional 8-bit data bus for accessing the nvSRAM Chip Enable: The active low E input selects the device Write Enable: The active low W enables data on the DQ pins to be written to the address location latched by the falling edge of E Output Enable: The active low G input enables the data output buffers during read cycles. De-asserting G high caused the DQ pins to tri-state. Power: 3.3V, +0.3V Hardware Store Busy: When low this output indicates a Store is in progress. When pulled low external to the chip, it will initiate a nonvolatile STORE operation. A weak pull up resistor keeps this pin high if not connected. (Connection Optional). AutoStore Capacitor: Supplies power to nvSRAM during power loss to store data from SRAM to nonvolatile storage elements. Ground
VCAP VSS
Power Supply Power Supply
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STK14C88-3
ABSOLUTE MAXIMUM RATINGSa
Voltage on Input Relative to Ground . . . . . . . . . . . . . -0.5V to 7.0V Voltage on Input Relative to VSS . . . . . . . . . . -0.6V to (VCC + 0.5V) Voltage on DQ0-7 or HSB . . . . . . . . . . . . . . . -0.5V to (VCC + 0.5V) Temperature under Bias . . . . . . . . . . . . . . . . . . . . . -55C to 125C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C Power Dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1W DC Output Current (1 output at a time, 1s duration) . . . . . . . 15mA
Note a: Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
NF (SOP-32) PACKAGE THERMAL CHARACTERISTICS
jc 5.4 C/W; ja 44.3 [0fpm], 37.9 [200fpm], 35.1 C/W [500fpm].
WF (PDIP-32) PACKAGE THERMAL CHARACTERISTICS
jc ND; ja 40 [0fpm], 34.5 [200fpm], 32.3 C/W [500fpm].
DC CHARACTERISTICS
COMMERCIAL SYMBOL ICC1b ICC2c ICC3b ICC4c ISB1d ISB2d IILK IOLK VIH VIL VOH VOL VBL TA VCC VCAP NVC DATAR PARAMETER MIN Average VCC Current Average VCC Current during STORE Average VCC Current at tAVAV = 200ns 5V, 25C, Typical Average VCAP Current during AutoStore Cycle Average VCC Current (Standby, Cycling TTL Input Levels) VCC Standby Current (Standby, Stable CMOS Input Levels) Input Leakage Current Off-State Output Leakage Current Input Logic "1" Voltage Input Logic "0" Voltage Output Logic "1" Voltage Output Logic "0" Voltage Logic "0" Voltage on HSB Output Operating Temperature Operating Voltage Storage Capacitor Nonvolatile STORE operations Data Retention 0 3.0 54 1,000 100 2.2 VSS - .5 2.4 0.4 0.4 70 3.6 264 - 40 3.0 54 1,000 100 MAX 50 42 3 9 2 18 16 1 1 1 VCC + .5 0.8 2.2 VSS - .5 2.4 0.4 0.4 85 3.6 264 MIN MAX 52 44 3 9 2 19 17 1 1 1 VCC + .5 0.8 mA mA mA mA mA mA mA mA A A V V V V V C V F K Years @55 C INDUSTRIAL UNITS
(VCC = 3 - 3.6V)e
NOTES tAVAV = 35ns tAVAV = 45ns All Inputs Don't Care, VCC = max W (V CC - 0.2V) All Others Cycling, CMOS Levels All Inputs Don't Care tAVAV = 35ns, E VIH tAVAV = 45ns, E VIH E (V CC - 0.2V) All Others VIN 0.2V or (VCC - 0.2V) VCC = max VIN = VSS to VCC VCC = max VIN = VSS to VCC, E or G VIH All Inputs All Inputs IOUT = - 4mA except HSB IOUT = 8mA except HSB IOUT = 3mA
3.3V 0.3V 68 to 220F 20%, 4.7v Rated
Note b: ICC1 and ICC3 are dependent on output loading and cycle rate. The specified values are obtained with outputs unloaded. Note c: CC2 and ICC4 are the average currents required for the duration of the respective STORE cycles (tSTORE ) . Note d: E VIH will not produce standby current levels until any nonvolatile cycle in progress has timed out. Note e: VCC reference levels throughout this datasheet refer to VCC if that is where the power supply connection is made, or VCAP if VCC is connected to ground.
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STK14C88-3
AC TEST CONDITIONS
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to 3V Input Rise and Fall Times. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5ns Input and Output Timing Reference Levels . . . . . . . . . . . . . . . 1.5V Output Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Figure 1
CAPACITANCEf
SYMBOL CIN COUT PARAMETER Input Capacitance Output Capacitance
(TA = 25C, f = 1.0MHz)
MAX 5 7 UNITS pF pF CONDITIONS V = 0 to 3V V = 0 to 3V
Note f:
These parameters are guaranteed but not tested.
3.3V
317 Ohms OUTPUT 351 Ohms 30 pF INCLUDING SCOPE AND FIXTURE
Figure 1. AC Output Loading
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STK14C88-3
SRAM READ CYCLES #1 & #2
SYMBOLS NO. #1, #2 1 2 3 4 5 6 7 8 9 10 11 tELQV tAVAVg, tELEHg tAVQVh tGLQV tAXQXh tELQX tEHQZi tGLQX tGHQZi tELICCHf tEHICCLf Alt. tACS tRC tAA tOE tOH tLZ tHZ tOLZ tOHZ tPA tPS Chip Enable Access Time Read Cycle Time Address Access Time Output Enable to Data Valid Output Hold after Address Change Address Change or Chip Enable to Output Active Address Change or Chip Disable to Output Inactive Output Enable to Output Active Output Disable to Output Inactive Chip Enable to Power Active Chip Disable to Power Standby 0 35 0 13 0 45 5 5 13 0 15 35 35 15 5 5 15 PARAMETER MIN MAX 35 45 45 20 MIN MAX 45 ns ns ns ns ns ns ns ns ns ns ns STK14C88-3-35
(VCC = 3V - 3.6V)e
STK14C88-3-45 UNITS
Note g: W and HSB must be high during SRAM READ cycles. Note h: /O state assumes E and G < VIL and W > VIH; device is continuously selected. Note i: Measured 200mV from steady state output voltage.
SRAM READ CYCLE #1: Address Controlledg, h
2 tAVAV ADDRESS 5 tAXQX DQ (DATA OUT) 3 tAVQV
DATA VALID
SRAM READ CYCLE #2: E and G Controlledg
ADDR ESS t E LE H 1 tEL Q V
2 29
tEHAX 11 tEHI CC L 7 tEHQ Z
E
27
6 t ELQ X
G
t AV QV 4 t G L QV 9 tGH Q Z
3
8 tG L Q X DQ (D ATA OUT) 10 tELI CC H
DAT A VAL ID
AC T IVE
ICC
ST AND BY
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STK14C88-3
SRAM WRITE CYCLES #1 & #2
SYMBOLS NO. #1 #2 Alt. PARAMETER STK14C88-335 MIN MAX
(VCC = 3V - 3.6V)e
STK14C88-345 MIN MAX UNITS
12 13 14 15 16 17 18 19 20 21
tAVAV tWLWH tELWH tDVWH tWHDX tAVWH tAVWL tWHAX t WLQZ i, j tWHQX
tAVAV tWLEH tELEH tDVEH tEHDX tAVEH tAVEL tEHAX
tWC tWP tCW tDW tDH tAW tAS tWR tWZ tOW
Write Cycle Time Write Pulse Width Chip Enable to End of Write Data Set-up to End of Write Data Hold after End of Write Address Set-up to End of Write Address Set-up to Start of Write Address Hold after End of Write Write Enable to Output Disable Output Active after End of Write
35 25 25 12 0 25 0 0 13 5
45 30 30 15 0 30 0 0 15 5
ns ns ns ns ns ns ns ns ns ns
Note j: W is low when E goes low, the outputs remain in the high-impedance state. Note k: E or W must be VIH during address transitions. Note l: HSB must be high during SRAM WRITE cycles.
SRAM WRITE CYCLE #1: W Controlledk, l
12 tAVAV ADDRESS 14 tELWH E 17 tAVWH 13 tWLWH 15 tDVWH DATA IN 20 tWLQZ
PREVIOUS DATA DATA VALID
19 tWHAX
18 tAVWL W
16 tWHDX
DATA OUT
HIGH IMPEDANCE
21 tWHQX
SRAM WRITE CYCLE #2: E Controlledk, l
12 tAVAV ADDRESS 18 tAVEL E 14 tELEH 19 tEHAX
17 tAVEH W
13 tWLEH 15 tDVEH 16 tEHDX
DATA VALID HIGH IMPEDANCE
DATA IN DATA OUT
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HARDWARE MODE SELECTION
E W HSB A13 - A0 (hex) MODE I/O POWER NOTES
H L L X
X H L X
H H H L
X X X X
Not Selected Read SRAM Write SRAM Nonvolatile STORE
Output High Z Output Data Input Data Output High Z
Standby Active Active lCC2 m t
Note m: HSB STORE operation occurs only if an SRAM WRITE has been done since the last nonvolatile cycle. After the STORE (if any) completes, the part will go into standby mode, inhibiting all operations until HSB rises.
HARDWARE STORE CYCLE
SYMBOLS NO. Standard Alternate PARAMETER
(VCC = 3V - 3.6V)e
STK14C88-3 UNITS MIN MAX NOTES
22 23 24 25 26
tSTORE tDELAY tRECOVER tHLHX tHLBL
tHLHZ tHLQZ tHHQX
STORE Cycle Duration
10 1 700 15 300
ms
s
n n n, o
Time Allowed to Complete SRAM Cycle Hardware STORE High to Inhibit Off Hardware STORE Pulse Width Hardware STORE Low to STORE Busy
ns ns ns
Note n: E and G low and W high for output behavior. Note o: tRECOVER is only applicable after tSTORE is complete.
HARDWARE STORE CYCLE
25 tHLHX HSB (IN) 24 tRECOVER 22 tSTORE
HSB (OUT)
HIGH IMPEDANCE
26 tHLBL
HIGH IMPEDANCE
23 tDELAY DQ (DATA OUT)
DATA VALID DATA VALID
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STK14C88-3
AutoStore/POWER-UP RECALL
SYMBOLS NO. Standard Alternate PARAMETER MIN MAX
(VCC = 3V - 3.6V)e
STK14C88-3 UNITS NOTES
27 28 29 30 31 32
tRESTORE tSTORE tVSBL tDELAY VSWITCH VRESET tBLQZ tHLHZ
Power-up RECALL Duration
STORE Cycle Duration
550 10 300 1 2.7 2.95 2.4
s
p n, q l n
ms ns
s
Low Voltage Trigger (VSWITCH) to HSB Low Time Allowed to Complete SRAM Cycle Low Voltage Trigger Level Low Voltage Reset Level
V V
Note p: tRESTORE starts from the time VCC rises above VSWITCH. Note q: HSB is asserted low for 1s when VCAP drops through VSWITCH. If an SRAM WRITE has not taken place since the last nonvolatile cycle, HSB will be released and no STORE will take place.
AutoStore/POWER-UP RECALL
VCC 31 VSWITCH 32 VRESET
AutoStore
POWER-UP RECALL 27 tRESTORE HSB 30 tDELAY W 29 tVSBL 28 tSTORE
DQ (DATA OUT)
POWER-UP RECALL
BROWN OUT NO STORE (NO SRAM WRITES) NO RECALL (VCC DID NOT GO BELOW VRESET)
BROWN OUT AutoStore NO RECALL (VCC DID NOT GO BELOW VRESET)
BROWN OUT AutoStore RECALL WHEN VCC RETURNS ABOVE VSWITCH
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STK14C88-3
SOFTWARE STORE/RECALL MODE SELECTION
E W A13 - A0 (hex) MODE I/O POWER NOTES
L
H
0E38 31C7 03E0 3C1F 303F 0FC0 0E38 31C7 03E0 3C1F 303F 0C63
Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM Nonvolatile STORE Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM Nonvolatile RECALL
Output Data Output Data Output Data Output Data Output Data Output High Z Output Data Output Data Output Data Output Data Output Data Output High Z
Active
n, r, s, t
lCC2
L
H
Active
n, r, s, t
SOFTWARE-CONTROLLED STORE/RECALL CYCLEv
SYMBOLS NO. Standard Alternate PARAMETER STK14C88-335 MIN STORE/RECALL Initiation Cycle Time MAX
(VCC = 3V - 3.6V)e
STK14C88-345 MIN MAX UNITS NOTES
33 34 35 36 37
tAVAV tAVEL tELEH tELAX tRECALL
tRC tAS tCW
35 0 25 20 20
45 0 30 20 20
ns ns ns ns
s
n u, v u,v u, v
Address Set-up Time Clock Pulse Width Address Hold Time
RECALL Duration
The six consecutive addresses must be in the order listed. W must be high during all six consecutive E controlled cycles to enable a nonvolatile cycle. Note s: While there are 15 addresses on the STK14C88-3, only the lower 14 are used to control software modes. Note t: I/O state assumes G < VIL. Activation of nonvolatile cycles does not depend on state of G. Note u: The software sequence is clocked on the falling edge of E controlled READs without involving G (double clocking will abort the sequence). See application note:MA0002 http://www.simtek.com/attachments/AppNote02.pdf. Note v: The six consecutive addresses must be in the order listed in the Software STORE/RECALL Mode Selection Table: (0E38, 31C7, 03E0, 3C1F, 303F, 0FC0) for a STORE cycle or (0E38, 31C7, 03E0, 3C1F, 303F, 0C63) for a RECALL cycle. W must be high during all six consecutive cycles.
Note r:
SOFTWARE STORE/RECALL CYCLE: E CONTROLLEDv
tAVAV ADDRESS
34 ADDRESS #1 33
tAVAV
ADDRESS #6
33
tAVEL E
tELEH
35
tELAX
28 37 / tRECALL
36
tSTORE DQ (DATA
DATA VALID DATA VALID
HIGH IMPEDANCE
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STK14C88-3 nvSRAM OPERATION
The STK14C88-3 has two separate modes of operation: SRAM mode and nonvolatile mode. In SRAM mode, the memory operates as a standard fast static RAM. In nonvolatile mode, data is transferred from SRAM to nonvolatile elements (the STORE operation) or from nonvolatile elements to SRAM (the RECALL operation). In this mode SRAM functions are disabled.
POWER-UP RECALL
During power up, or after any low-power condition (VCAP < VRESET), an internal RECALL request will be latched. When VCAP once again exceeds the sense voltage of VSWITCH, a RECALL cycle will automatically be initiated and will take tRESTORE to complete. If the STK14C88-3 is in a WRITE state at the end of power-up RECALL, the SRAM data will be corrupted. To help avoid this situation, a 10K Ohm resistor should be connected either between W and system VCC or between E and system VCC.
NOISE CONSIDERATIONS
The STK14C88-3 is a high-speed memory and so must have a high-frequency bypass capacitor of approximately 0.1F connected between VCAP and VSS, using leads and traces that are as short as possible. As with all high-speed CMOS ICs, normal careful routing of power, ground and signals will help prevent noise problems.
SOFTWARE NONVOLATILE STORE
The STK14C88-3 software STORE cycle is initiated by executing sequential E controlled READ cycles from six specific address locations. During the STORE cycle an erase of the previous nonvolatile data is first performed, followed by a program of the nonvolatile elements. The program operation copies the SRAM data into nonvolatile memory. Once a STORE cycle is initiated, further input and output are disabled until the cycle is completed. Because a sequence of READs from specific addresses is used for STORE initiation, it is important that no other READ or WRITE accesses intervene in the sequence, or the sequence will be aborted and no STORE or RECALL will take place. To initiate the software STORE cycle, the following READ sequence must be performed:
1. 2. 3. 4. 5. 6. Read address Read address Read address Read address Read address Read address 0E38 (hex) 31C7 (hex) 03E0 (hex) 3C1F (hex) 303F (hex) 0FC0 (hex) Valid READ Valid READ Valid READ Valid READ Valid READ Initiate STORE cycle
SRAM READ
The STK14C88-3 performs a READ cycle whenever E and G are low and W and HSB are high. The address specified on pins A0-14 determines which of the 32,768 data byte will be accessed. When the READ is initiated by an address transition, the outputs will be valid after a delay of tAVQV (READ cycle #1). If the READ is initiated by E or G, the outputs will be valid at tELQV or at tGLQV, whichever is later (READ cycle #2).The data outputs will repeatedly respond to address changes within the tAVQV access time without the need for transitions on any control input pins, and will remain valid until another address change or until E or G is brought high, or W or HSB is brought low.
SRAM WRITE
A WRITE cycle is performed whenever E and W are low and HSB is high. The address inputs must be stable prior to entering the WRITE cycle and must remain stable until either E or W goes high at the end of the cycle. The data on the common I/O pins DQ0-7 will be written into the memory if it is valid tDVWH before the end of a W controlled WRITE or tDVEH before the end of an E controlled WRITE. It is recommended that G be kept high during the entire WRITE cycle to avoid data bus contention on common I/O lines. If G is left low, internal circuitry will turn off the output buffers tWLQZ after W goes low.
The software sequence must be clocked with E controlled READs. Once the sixth address in the sequence has been entered, the STORE cycle will commence and the chip will be disabled. It is important that READ cycles and not WRITE cycles be used in the sequence, although it is not necessary that G be low for the sequence to be valid. After the tSTORE cycle time has been fulfilled, the SRAM will again be activated for READ and WRITE operation.
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STK14C88-3
SOFTWARE NONVOLATILE RECALL
A software RECALL cycle is initiated with a sequence of READ operations in a manner similar to the software STORE initiation. To initiate the RECALL cycle, the following sequence of E controlled READ operations must be performed:
1. 2. 3. 4. 5. 6. Read address Read address Read address Read address Read address Read address 0E38 (hex) 31C7 (hex) 03E0 (hex) 3C1F (hex) 303F (hex) 0C63 (hex) Valid READ Valid READ Valid READ Valid READ Valid READ Initiate RECALL cycle
68 F 6V, 20% + 0.1 F Bypass 10kO* 10kO
10K 10K? 10K 10K?
1
32 31 30
Internally, RECALL is a two-step procedure. First, the SRAM data is cleared, and second, the nonvolatile information is transferred into the SRAM cells. After the tRECALL cycle time the SRAM will once again be ready for READ and WRITE operations. The RECALL operation in no way alters the data in the nonvolatile elements. The nonvolatile data can be recalled an unlimited number of times.
16
17
Figure 2: AutoStore Mode *If HSB is not used, it should be left unconnected.
AutoStore INHIBIT MODE
If an automatic STORE on power loss is not required, then Vcc can be tied to ground and system power applied to VCAP (Figure 3). This is the AutoStore Inhibit mode, in which the AutoStore function is disabled. If the STK14C88-3 is operated in this configuration, references to Vcc should be changed to VCAP throughout this data sheet. In this mode, STORE operations may be triggered through software control. It is not permissible to change between these three options "on the fly."
AutoStore MODE
The STK14C88-3 can be powered in one of three modes. During normal AutoStore operation, the STK14C883 will draw current from VCC to charge a capacitor connected to the VCAP pin. This stored charge will be used by the chip to perform a single STORE operation. After power up, when the voltage on the VCAP pin drops below VSWITCH, the part will automatically disconnect the VCAP pin from VCC and initiate a STORE operation. Figure 2 shows the proper connection of capacitors for automatic store operation. A charge storage capacitor having a capacity of between 68F and 220F ( 20%) rated at 4.7V should be provided. In order to prevent unneeded STORE operations, automatic STOREs as well as those initiated by externally driving HSB low will be ignored unless at least one WRITE operation has taken place since the most recent STORE or RECALL cycle. Softwareinitiated STORE cycles are performed regardless of whether a WRITE operation has taken place. If the power supply drops faster than 20 s/volt before VCC reaches VSWITCH, then a 1 ohm resistor should be inserted between VCC and the system supply to avoid momentary excess of current between Vcc and Vcap.
0.1F Bypass
1
32 31 30
16
17
Figure 3: AutoStore Inhibit Mode *If HSB is not used, it should be left unconnected.
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STK14C88-3
HSB OPERATION
The STK14C88-3 provides the HSB pin for controlling and acknowledging the STORE operations. The HSB pin can be used to request a hardware STORE cycle. When the HSB pin is driven low, the STK14C88-3 will conditionally initiate a STORE operation after tDELAY; an actual STORE cycle will only begin if a WRITE to the SRAM took place since the last STORE or RECALL cycle. The HSB pin has a very resistive pullup and is internally driven low to indicate a busy condition while the STORE (initiated by any means) is in progress. Pull up this pin with an external 10K ohm resistor to VCAP if HSB is used as a driver.
SRAM READ and WRITE operations that are in
BEST PRACTICES
nvSRAM products have been used effectively for over 15 years. While ease-of-use is one of the product's main system values, experience gained working with hundreds of applications has resulted in the following suggestions as best practices: * The non-volatile cells in an nvSRAM are programmed on the test floor during final test and quality assurance. Incoming inspection routines at customer or contract manufacturer's sites will sometimes reprogram these values. Final NV patterns are typically repeating patterns of AA, 55, 00, FF, A5, or 5A. End product's firmware should not assume an NV array is in a set programmed state. Routines that check memory content values to determine first time system configuration, cold or warm boot status, etc. should always program a unique NV pattern (e.g., complex 4-byte pattern of 46 E6 49 53 hex or more random bytes) as part of the final system manufacturing test to ensure these system routines work consistently. * Power up boot firmware routines should rewrite the nvSRAM into the desired state (autostore enabled, etc.). While the nvSRAM is shipped in a preset state, best practice is to again rewrite the nvSRAM into the desired state as a safeguard against events that might flip the bit inadvertently (program bugs, incoming inspection routines, etc.). * The Vcap value specified in this datasheet includes a minimum and a maximum value size. Best practice is to meet this requirement and not exceed the max Vcap value because the nvSRAM internal algorithm calculates Vcap charge time based on this max Vcap value. Customers that want to use a larger Vcap value to make sure there is extra store charge and store time should discuss their Vcap size selection with Simtek to understand any impact on the Vcap voltage level at the end of a tRECALL period.
progress when HSB is driven low by any means are given time to complete before the STORE operation is initiated. After HSB goes low, the STK14C88-3 will continue SRAM operations for tDELAY. During tDELAY, multiple SRAM READ operations may take place. If a WRITE is in progress when HSB is pulled low it will be allowed a time, tDELAY, to complete. However, any SRAM WRITE cycles requested after HSB goes low will be inhibited until HSB returns high. The HSB pin can be used to synchronize multiple STK14C88-3s while using a single larger capacitor. To operate in this mode the HSB pin should be connected together to the HSB pins from the other STK14C88-3s. An external pull-up resistor to +3.3V is required since HSB acts as an open drain pulldown. The VCAP pins from the other STK14C88-3 parts can be tied together and share a single capacitor. The capacitor size must be scaled by the number of devices connected to it. When any one of the STK14C88-3s detects a power loss and asserts HSB, the common HSB pin will cause all parts to request a STORE cycle (a STORE will take place in those STK14C88-3s that have been written since the last nonvolatile cycle). During any STORE operation, regardless of how it was initiated, the STK14C88-3 will continue to drive the HSB pin low, releasing it only when the STORE is complete. Upon completion of the STORE operation the STK14C88-3 will remain disabled until the HSB pin returns high. If HSB is not used, it should be left unconnected.
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STK14C88-3
PREVENTING STORES
The STORE function can be disabled on the fly by holding HSB high with a driver capable of sourcing 30mA at a VOH of at least 2.2V, as it will have to overpower the internal pull-down device that drives HSB low for 20s at the onset of a STORE. When the STK14C88-3 is connected for AutoStore operation (system VCC connected to VCC and a 68F capacitor on VCAP) and VCC crosses VSWITCH on the way down, the STK14C88-3 will attempt to pull HSB low; if HSB doesn't actually get below VIL, the part will stop trying to pull HSB low and abort the STORE attempt. If the chip enable duty cycle is less than 100%, only standby current is drawn when the chip is disabled. The overall average current drawn by the STK14C88-3 depends on the following items: 1) CMOS vs. TTL input levels; 2) the duty cycle of chip enable; 3) the overall cycle rate for accesses; 4) the ratio of READs to WRITEs; 5) the operating temperature; 6) the Vcc level; and 7) I/O loading.
100
Average Active Current (mA)
80
HARDWARE PROTECT
The STK14C88-3 offers hardware protection against inadvertent STORE operation and SRAM WRITEs during low-voltage conditions. When VCAP < VSWITCH, all externally initiated STORE operations and SRAM WRITEs will be inhibited.
60
40 TTL 20 CMOS 0 50 100 150 Cycle Time (ns) 200
LOW AVERAGE ACTIVE POWER
The STK14C88-3 draws significantly less current when it is cycled at times longer than 50ns. Figure 4 shows the relationship between ICC and READ cycle time. Worst-case current consumption is shown for both CMOS and TTL input levels (commercial temperature range, VCC = 3.6V, 100% duty cycle on chip enable). Figure 5 shows the same relationship for WRITE cycles.
Figure 4: Icc (max) Reads
100
Average Active Current (mA)
80
60 TTL CMOS 20
40
0 50 100 150 Cycle Time (ns) 200
Figure 5: Icc (max) Writes
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STK14C88-3
Commercial and Industrial Ordering Information
STK14C88-3 N F 45 I TR
Packaging Option
Blank = Tube TR = Tape and Reel
Temperature Range
Blank = Commercial (0 to 70C) I = Industrial (-40 to 85C)
Access Time
35 = 35ns 45 = 45ns
Lead Finish
F = 100% Sn (Matte Tin)
Package
N = Plastic 32-pin 300 mil SOIC W = Plastic 32-pin 600 mil DIP
Document Control #ML0015 Rev 2.0 Feb, 2008
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STK14C88-3
ORDERING INFORMATION
Part Number STK14C88-3WF35 STK14C88-3WF45 STK14C88-3NF35 STK14C88-3NF45 STK14C88-3NF35TR STK14C88-3NF45TR STK14C88-3WF35I STK14C88-3WF45I STK14C88-3NF35I STK14C88-3NF45I STK14C88-3NF35ITR STK14C88-3NF45ITR Description 3.3V 32Kx8 AutoStore nvSRAM PDIP32-600 3.3V 32Kx8 AutoStore nvSRAM PDIP32-600 3.3V 32Kx8 AutoStore nvSRAM SOP32-300 3.3V 32Kx8 AutoStore nvSRAM SOP32-300 3.3V 32Kx8 AutoStore nvSRAM SOP32-300 3.3V 32Kx8 AutoStore nvSRAM SOP32-300 3.3V 32Kx8 AutoStore nvSRAM PDIP32-600 3.3V 32Kx8 AutoStore nvSRAM PDIP32-600 3.3V 32Kx8 AutoStore nvSRAM SOP32-300 3.3V 32Kx8 AutoStore nvSRAM SOP32-300 3.3V 32Kx8 AutoStore nvSRAM SOP32-300 3.3V 32Kx8 AutoStore nvSRAM SOP32-300 Access Times 35 ns access time 45 ns access time 35 ns access time 45 ns access time 35 ns access time 45 ns access time 35 ns access time 45 ns access time 35 ns access time 45 ns access time 35 ns access time 45 ns access time Temperature Commercial Commercial Commercial Commercial Commercial Commercial Industrial Industrial Industrial Industrial Industrial Industrial
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STK14C88-3 Package Diagrams
32-pin 300 mil SOIC Gull Wing
0.292 7.42 0.300 7.60
(
)
0.405 10.29 0.419 10.64
(
)
Pin 1 Index
.050 (1.27)
0.810 20.57 0.822 20.88
(
)
BSC
0.026 0.66 0.032 0.81
(
)
0.090 2.29 0.100 2.54
()
0.086 0.090 2.18 ( 2.29)
0.12 0.22 0.004 0.10 0.010 0.25
0.014 0.36 0.020 0.51
()
()
0.006 0.013
()
0.021 0.041
0.15 0.32
0 8 0.53 ( 1.04 )
o o
DIM = INCHES DIM = mm
MIN MAX
MIN ( MAX )
Document Control #ML0015 Rev 2.0 Feb, 2008
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STK14C88-3
32-pin 600 mil PDIP
Pin 1 Index
.530 .550
( 13.46 ) 13.97
.070 .080
( 1.78 ) 2.03
1.645 1.655 ---.190
( 41.78 ) 42.04
.015 ---.125 .135 3.18 (3.43)
( 4.83 )
----
(0.38) ----
.016 .020
()
0.41 0.51
.045 .055
()
1.14 1.40
.100 (2.54) BSC
.600 .625
( 15.24 ) 15.88
DIM = INCHES DIM = MM MIN MAX MIN ( MAX)
0o 15o
.008 .012
(
0.20 0.30
)
.600 (15.24) BSC
Document Control #ML0015 Rev 2.0 Feb, 2008
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STK14C88-3
Document Revision History
Revision
Date January 2003 February 2003 September 2003 November 2003 January 2006
Summary Added 35 nsec device; added HSB operation; current limiting resistor added to Vcc for extreme power-off slew rate Added 48 SSOP package Added lead-free lead finish Modified pin assignments on 48 SSOP package Removed 48 pin SSOP package. Removed 55 ns product offering. Added previously unspecified NVC and DATAR specifications to DC Characteristics. Removed Leaded Lead Finish Add Tape Reel Ordering Options Add Product Ordering Code Listing Add Package Drawings Reformat Entire Document extend definition of tHZ (#7) update fig. SRAM READ CYCLE #2, SRAM WRITE CYCLE #1, Note r, Note u and Note v to clarify product usage Page 1: in the block diagram and elsewhere in the document, removed the "x" from Vccx. Page 3: added thermal characteristics. Page 4: in Note g below the SRAM Read Cycles #1 and #2 table, revised note g by deleting "and low during SRAM WRITE cycles; in SRAM Read Cycles #1 & #2 table, revised description for tELQX; changed Symbol #2 to tELEH for Read Cycle Time; updated SRAM Read Cycle #2 timing diagram; and changed title to add G controlled. Page 7: in Hardware Store Cycle table, removed footnote i for notes 22 and 23. Page 8: in Software Store/Recall Mode Selection table, added footnote n to both rows. Page 11: under HSB Operation, revised first paragraph to read "The HSB pin has a very resistive pullup..." Page 12: added best practices section. Page 15: added access times column to the Ordering codes.
0.0 0.1 0.2 0.3 0.4
0.5 0.6
March 2006 February 2007
0.7
July 2007
2.0
February 2008
SIMTEK STK14C88-3 Datasheet, February 2008 Copyright 2008, Simtek Corporation. All rights reserved. This datasheet may only be printed for the expressed use of Simtek Customers. No part of the datasheet may be reproduced in any other form or means without the express written permission from Simtek Corporation. The information contained in this publication is believed to be accurate, but changes may be made without notice. Simtek does not assume responsibility for, or grant or imply any warranty, including MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE regarding this information, the product or its use. Nothing herein constitutes a license, grant or transfer of any rights to any Simtek patent, copyright, trademark, or other proprietary right.
Document Control #ML0015 Rev 2.0 Feb, 2008
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